[GreatFET] Cortex M0 Coprocessor Plans

[Evan]

As the LPC4330 has a coprocessor (cortex m0) I was curious to see how
it's being used in the greatfet firmware. This led to finding this
comment:

> TODO: include libgreat's m0_coprocessor include, to allow m0 code to
> be added

Does this mean it's currently not used?

What are the plans for the coprocessor?

Any thoughts on how to expose its functionality to the python API? Since
most I/O is accessible from the m0, we could clone the i2c bus to
gf.m0.i2c for example. With that, a researcher could drive i2c with the
m0 and simultaneously capture gpio with logic analyzer on the m4. Would
this give any real benefit?

Another idea is to sniff SPI, i2c, or for some other pattern on gpio,
then trigger the m4 to capture logic dumps until some specified stop
pattern. This could be optimized to capture in a ring buffer until start
condition, then pipe out the data until end condition.

Just some random thoughts, curious what others are considering here with
the awesome power of two processors.

Evan